1. Field of the Invention
The present invention relates to an over-sampling A/D converting circuit, in particular, an over-sampling A/D converting circuit for processing analog video signals.
2. Description of Related Art
In recent years, television receivers or monitoring devices have advanced toward upsizing of their screens for displaying a picture. In such television receivers, a problem about a displayed image such as weak video noise comes to the surface albeit being ignorable on a small screen. To that end, a higher image quality is required.
In general, a composite video signal as shown in FIG. 4 is input to the television receiver. As shown in FIG. 4, the composite video signal includes a video signal obtained by multiplexing a luminance signal (Y signal) with a chrominance signal (C signal), a burst signal used as a reference for the chrominance signal, and a sync signal for synchronizing signals. Further, the composite video signal has frequency characteristics as shown in FIG. 5. The frequency thereof falls within a frequency band from 0 to fmax (maximum frequency). The luminance signal is also within this frequency band. The chrominance signal is superimposed on a color subcarrier having a frequency fsc (color subcarrier frequency) to obtain a signal of a frequency within a predetermined frequency band where the frequency fsc is set at the center. This frequency fsc is a frequency of the burst signal of FIG. 4. A color television system (color television format) varies from one composite video signal to another. Depending on the color television system, the values of the frequencies fmax or fsc vary. As regards an NTSC color television system, for example, fmax=4.2 MHz and fsc=3.58 MHz. For a PAL color television system, fmax=6 MHz and fsc=4.43 MHz. In the video signals, there is a component video signal where the luminance signal is separated from the chrominance signal or color difference signal.
In digital video signal processing for processing a video signal, there are two kinds of system clock: a burst lock clock the phase of which is locked in the phase of the frequency fsc of the video signal; and a horizontal synchronizing lock clock the phase of which is locked in the phase of the horizontal synchronizing signal. A burst lock clock processing for the composite video signal enables high-accuracy separation between the Y signal and the C signal (Y/C separation), and a horizontal synchronizing lock clock processing for the composite video signal does not require a complicated circuit configuration. A general clock frequency is 4 fsc which is 4 times higher than the frequency fsc. In the component signal having no color subcarrier, 13.5 MHz that is a frequency of the horizontal synchronizing lock signal, is generally used.
Receiving the composite video signal, the television receiver separates the video signal into a luminance signal and a chrominance signal (Y/C separation) to demodulate the chrominance signal (C demodulation) and then displays a picture. In recent years, digital circuits are used for the above process to execute the Y/C separation or C demodulation through the digital signal processing. Therefore, an A/D converter for converting an analog video signal into a digital signal is generally provided upstream from a Y/C separation circuit. This A/D converter carries out the A/D conversion using 4 fsc as a sampling frequency.
However, a weak video noise may annoy a viewer on a large screen of a monitor device due to the A/D conversion.
This results from aliasing noise that would occur during the A/D conversion. The aliasing noise is described hereinbelow. In the A/D conversion, as long as the sampling frequency is at least twice the input signal frequency, the signal can be completely restored to the original signal. That is, the above frequency band is such a band as ensures information carried on the signal of ½ or less of the sampling frequency (Nyquist frequency). For example, if the sampling frequency is 4 fsc, as shown in FIG. 6, 2 fsc that is ½ of 4 fsc is the Nyquist frequency. Upon the A/D conversion with 4 fsc of sampling frequency, if there is a frequency component higher than 2 fsc of Nyquist frequency ((a) in FIG. 6), a signal component appears at a position ((b) of FIG. 6) symmetric about the Nyquist frequency to the position (a) (fold-back). Then, apart ((c) of FIG. 6) of the folded signal component frequency is superimposed on the original signal into the aliasing noise. As a conventional circuit for reducing the aliasing noise, for example, Japanese Unexamined Patent Publication No. 62-287716 discloses an over-sampling A/D converting circuit using a frequency band limiting filter.
FIG. 7 shows the configuration of a conventional video signal processing circuit byway of example. In this conventional video signal processing circuit, the conventional over-sampling A/D converting circuit is provided upstream from the Y/C separation circuit for the purpose of reducing the aliasing noise.
The conventional video signal processing circuit includes an analog low pass filter (LPF) 702 composed of an analog circuit, an over-sampling A/D converting circuit 701 and a Y/C separation circuit 703 composed of a digital circuit. Further, the conventional over-sampling A/D converting circuit 701 includes an A/D converter 711, a digital LPF 712, a down-sampling circuit 713, a clock generation phase locked loop (PLL) 715, and a ½ divider circuit 716.
In the conventional over-sampling A/D converting circuit 701, the A/D converter 711 executes the A/D conversion on a video signal input through the analog LPF 702 using the sampling frequency of 8 fsc. The digital LPF 712 limits the band using 2 fsc that is the Nyquist frequency of 4 fsc as a cut-off frequency. The down-sampling circuit 713 down-samples (thins out) the input signal frequency into the sampling frequency of 4 fsc to be output to the Y/C separation circuit 703. The Y/C separation circuit 703 separates the video signal with the sampling frequency of 4 fsc into a Y signal and a C signal.
The clock generation PLL 715 generates a clock at which the A/D converter 711, the digital LPF 712, and the down-sampling circuit 713 operate. The clock generation PLL 715 oscillates 8 fsc as a sampling clock frequency of the A/D converter 711. The ½ divider circuit 716 divides the frequency 8 fsc oscillated by the clock generation PLL 715 into ½ to generate a clock of 4 fsc as the sampling frequency of the down-sampling circuit 713.
The digital LPF 712 is so designed as to operate with the cut-off frequency of 2 fsc based on the clock of 8 fsc generated with the clock generation PLL 715. Then, the digital LPF 712 eliminates the signal component not lower than the Nyquist frequency to reduce the aliasing noise.
However, the conventional over-sampling A/D converting circuit 701 of FIG. 7 has a problem in that the noise cannot be eliminated depending on the color television system, leading to a low S/N ratio (signal-to-noise ratio). Accordingly, in the case where the output signal from the conventional over-sampling A/D converting circuit 701 is subjected to Y/C separation to display a picture, interference due to a noise occurs to deteriorate an image quality.
In other words, since the frequency fsc (color subcarrier frequency) varies from one color television system to another as mentioned above, the frequency of 8 fsc oscillated from the clock generation PLL 715 varies depending on the color television system. The digital LPF 712 is so designed as to have predetermined filter characteristics based on the input clock. Hence, if the frequency fsc varies, the filter characteristics of the digital LPF 712 accordingly change. As a result, the filter characteristics vary depending on the color television system. The cut-off frequency is different from a desired Nyquist frequency, making it impossible to accurately eliminate the aliasing noise.